Interfaces & Buses & I/Os

Dy 4 Systems, a business unit of Force Computers, provides mission-critical, open-architecture embedded computing solutions for aerospace and defense industry applications. To support its commitment to continuous improvement, Dy 4 implemented an SAP enterprise system. As a result, the company needed to migrate its existing packing label printing from a standalone process into its new R/3 environment. Printronix developed a complete solution that included the T5304 thermal printer and the standard Printronix Direct SAP R/3 Interface. tech news

High-speed link (HSL) is the name of the system internal bus technology of the latest iSeries servers that connects system processors to industry-standard PCI buses. As faster processors, larger cache, faster memory, a super-fast cross-bar switch complex, faster DASD, and much faster IOPs and IOAs continue to emerge, the HSL bus infrastructure provides more speed, capacity, flexibility, and power for today's iSeries servers. iSeries servers use HSL loops to provide expandability and connectivity for iSeries processors, towers, and external xSeries for iSeries adapters. This paper discusses HSL loop support, configuration, rules, and other considerations for the iSeries Models 270, 800, 810, 820, 825, 830, 840, 870, and 890 systems. tech news

This white paper details the 915G/915GV Express chipset GMCH memory configurations and organization. The Intel 915G/915GV Express chipset Graphics Memory Controller Hub (GMCH) is Intel's first dual-channel DDR/DDR2 Memory Controller Hub with Intel Flex Memory Technology. Intel has enhanced its memory architecture design to allow for maximum configuration flexibility while providing optimal performance when combined with DDR2-533 and an Intel Pentium 4 processor in the Land Grid Array 775 (LGA775) package with 800 MHz front side bus. tech news

This paper guides and assists one in selecting the correct server configuration for the selected Domino system, whether the system is for Web, application, or mail hosting. This paper provides performance tuning techniques and best practices available for Lotus Domino 6.5 running on IBM eServer xSeries and BladeCenter systems. It also describes the Domino network design, operating system, and disk I/O subsystem, with hints and tips to help one investigate and solve performance bottlenecks on the server. tech news

The PMB-2.2.1 benchmark was completed on POWER4+ platforms p690+ and p655+. Point-to-point performance was measured between two processes within the same node (memory performance), or between two nodes (network performance). The performance was measured in MBytes/s per process (send+recv) in units of microseconds. The MPI-I output results, without modification, are shown in graphical format in this paper. tech news