Memory Components

DDR SDRAMs break with the traditional system synchronous clocking approach, that uses only one global and skewless clock distribution network. The application of DDR SDRAMs requires a source synchronous clocking concept that simultaneously transmits clock and data signals from the memory controller to the DDR SDRAM devices. From the perspective of this source synchronous clocking concept, many timing problems disappear and using DDR SDRAMs is quite straightforward. This paper discusses a clocking strategy for a DDR SDRAM Controller IP implemented in a Xilinx Virtex-II-Pro FPGA. tech news

This paper describes a Parallel Vector Access unit PVA), the vector memory subsystem that efficiently "gathers" sparse, strided data structures in parallel on a multibank SDRAM memory. We have validated our PVA design via gate-level simulation, and have evaluated its performance via functional simulation and formal analysis. On unit-stride vectors, PVA performance equals or exceeds that of an SDRAM system optimized for cache line fills. On vectors with larger strides, the PVA is up to 32.8 times faster. tech news

This paper is provided to highlight the issues that need to be considered, and to discuss different ways to use the SDRAM interface. The SDRAM is divided up at the lowest level in to rows and columns. To access an element in an SDRAM module, first the row is opened and is then said to be the active row, secondly a column with in that row is selected and the data output from its location. This setting up of the SDRAM can take several clock cycles and every access will require the appropriate row to be activated. tech news

Processors such as StrongARM and memory such as SDRAM enable efficient execution of multiple loads and stores in a single instruction. This is particularly useful in connection with register allocation where spill code may need to save and restore multiple registers. Until now, there has been no effective strategy for utilizing this to its full potential. This paper investigates the use of SDRAM for optimization of spill code. The core of the problem is to arrange the variables in the spill area such that loading to and storing from the SDRAM is optimally efficient. tech news

The Au1000, Au1500 and Au1100 (Au1x00) processors each feature an integrated, high-performance SDRAM controller for connecting to 32-bit wide external SDRAM memory. This paper describes the performance characteristics of the SDRAM controller and techniques for optimizing SDRAM performance. The SDRAM controller on an Au1x00 processor supports three ranks of 32-bit wide SDRAM. A rank is a physical grouping of SDRAM devices, all tied to the same chip select. tech news