ProcessorsIBM eServer zSeries 990 Cryptographic Coprocessor Configuration This paper provides information on the PCI X Cryptographic Coprocessor (PCIXCC) and the PCI Cryptographic Accelerator (PCICA) on a z990 server. It describes cryptographic domains and z990 configuration rules considering the increased number of logical partitions. It reviews items that should be taken into consideration when planning for non-disruptive installation of PCICA and PCIXCC features.
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Maximizing Resources through Efficient Overall Operations To help ease of mind, there are products committed to helping companies become more efficient and responsive while improving accessibility and security. From access strategies and office productivity solutions to mobile capabilities, there is innovative technology options available to meet issues today and manage mission-critical resources for the long term. This white paper is designed to explain how you can make these options a part of your organization to help it achieve its full potential.
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SDRAM Performance on Alchemy Au1000, Au1100 and Au1500 Processors From AMD The Au1000, Au1500 and Au1100 (Au1x00) processors each feature an integrated, high-performance SDRAM controller for connecting to 32-bit wide external SDRAM memory. This paper describes the performance characteristics of the SDRAM controller and techniques for optimizing SDRAM performance. The SDRAM controller on an Au1x00 processor supports three ranks of 32-bit wide SDRAM. A rank is a physical grouping of SDRAM devices, all tied to the same chip select.
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Transparent Data-Memory Organizations for Digital Signal Processors Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system - the DRAM and dual tagless SRAMs - are referenced through completely separate segments of the address space. The recent trend of programming DSPs in high-level languages instead of assembly code has exposed this memory model as a potential weakness, as the model makes for a poor compiler target. In many of today's high-performance DSPs this non-uniform model is being replaced by a uniform model - a transparent organization like that of most general-purpose systems, in which all memory structures share the same address space as the DRAM system.
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Uniprocessor Virtual Memory Without TLBs This paper presents a feasible study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simple, smaller, and more energy-efficient at little or no cost in performance. The purpose of this paper is to describe the design and quantify its performance impact.
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